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Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
FEATURES
* Multiplexed parallel I/O ports * Separate serial input and output * Sign extend function * 3-State outputs for bus applications * Direct Overriding Clear
DESCRIPTION
The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend, and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the registers. The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A Low signal on RE enables shifting or parallel loading, while a High signal enables the hold mode. A High signal on S/P enables shift right, while a Low signal disables the 3-State output buffers and enables parallel loading. In the shift right mode a High signal on SE enables serial entry from either D0 or D1, as determined by the S input. A Low signal on SE enables shift right, but Q7 reloads its contents, thus performing the sign extend function. A High signal on OE disables the 3-State output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.
PIN CONFIGURATION
RE S/P D0 I/O0 I/O2 I/O4 I/O6 OE MR 1 2 3 4 5 6 7 8 9 20 VCC 19 S 18 SE 17 D1 16 I/O1 15 I/O3 14 I/O5 13 I/O7 12 Q7 11 CP
GND 10
SF00874
TYPE 74F322
TYPICAL fMAX 125MHz
TYPICAL SUPPLY CURRENT (TOTAL) 60mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F322N N74F322D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0, D1 S SE CP S/P RE MR OE Q7 I/On Serial data inputs Serial data select input Sign Extend input Clock Pulse input (Active rising edge) Serial (High) or Parallel (Low) mode control input Register Enable input (Active Low) Asynchronous Master Reset input (Active Low) Output Enable input (Active Low) Bi-state serial output Multiplexed parallel data inputs or DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/2.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 3.5/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/1.2mA 20A/1.8mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 70A/0.6mA 3.0mA/24mA
3-State parallel outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High State and 0.6mA in the Low state.
1988 Apr 22
1
853-0366 93020
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC SYMBOL
3 17
LOGIC SYMBOL (IEEE/IEC)
9 8 1 2 11 18 19 3 SRG8 R 2EN15 G3 3M1[SHIFT] 3M2[PAR LOAD] C6/1 G4 8, 4, 1, 6D G5 8, 5, 1, 6D 8, 4, 1, 6D 2, 6D 7, 15 16 5 15 6 14 7 13 2, 6D 12, 13 Z14 12 2, 96D 8, 15 Z8 Z7
19 1 2 18 11 8 9
S RE S/P SE CP OE MR I/O0 I/O1
D0
D1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Q7
17 4
VCC = Pin 20 GND = Pin 10
4
16
5
15
6
14
7
13
12
SF00875
SF00876
FUNCTION TABLE
INPUTS MR L L H H H H H X X * H L NC X Z I0-I7 = = = = = = = = RE H X L L L L H S/P X H L H H H X SE X X X H H L X S X X X L H X X OE* L L X L L L L CP X X X I/O0 L L I0 D0 D1 O0 NC I/O1 L L I1 O0 O0 O0 NC I/O2 L L I2 O1 O1 O1 NC I/O3 L L I3 O2 O2 O2 NC INPUTS I/O4 L L I4 O3 O3 O3 NC I/O5 L L I5 O4 O4 O4 NC I/O6 L L I6 O5 O5 O5 NC I/O7 L L I7 O6 O6 O6 NC Q7 L L I7 O6 O6 O6 NC OPERATING MODE Clear Parallel load Shift right Sign extend Hold
D0-D7 = O0-O7 = =
L L X X X X Z Z Z Z Z Z Z Z NC 3-State X X X X H Z Z Z Z Z Z Z Z NC When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not affected. High voltage level Low voltage level No change Don't care High impedance "off" state Low-to-High clock transition The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are isolated from the I/O terminal. The level of the steady state inputs to the serial multiplexer input. The level of the respective Qn flip-flop prior to the last clock Low-to-High transition. Not a Low-to-High clock transition
1988 Apr 22
2
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC DIAGRAM
OE RE 8 1
S/P D1 S D0
2 17 19 3
18 SE
CP D R
Q Q
4
I/O0
CP D R
Q Q
16
I/O1
CP D R
Q Q
5
I/O2
CP D R
Q Q
15
I/O3
CP D R
Q Q
6
I/O4
CP D R
Q Q
14
I/O5
CP D R
Q Q
7
I/O6
12 Q7 CP D R MR VCC = Pin 20 GND = Pin 10 CP 9 11 Q Q 13 I/O7
SF00877
1988 Apr 22
3
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature Q7 I/On PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +5.5 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Q7 I/On Low-level output current Operating free-air temperature range Q7 I/On 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 -3 20 24 70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA mA mA C UNIT
IOL Tamb
1988 Apr 22
4
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 2.4 2.7 3.3 0.38 0.35 -0.73 0.55 0.50 -1.2 100 1 20 -1.8 VCC = MAX, VI = 0.5V -1.2 -0.6 VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX ICCH ICC Supply current (total) ICCL ICCZ VCC = MAX -60 50 60 65 70 -0.6 -150 75 90 95 3.4 TYP2 MAX UNIT V V V V V V V A mA A mA mA mA A mA mA mA mA mA
Q7 VOH High-level output voltage I/On
VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN
IOH = -1mA
IOH = -3mA
VOL VIK II IIH IIL
Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current SE Low-level input current S others others I/On
IOL = MAX
VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 5.5V VCC = MAX, VI = 2.7V
IIH + IOZH IIL + IOZL IOS
Off-state output current High-level voltage applied Off-state output current Low-level voltage applied Short-circuit output current3
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1988 Apr 22
5
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to I/On Propagation delay CP to Q7 Propagation delay MR to I/On Propagation delay MR to Q7 Output Enable time OE to I/On Output Disable time OE to I/On Output Disable time S/P to I/On Output Disable time S/P to I/On Output Disable time RE to I/On Output Disable time RE to I/On Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 4 Waveform 5 110 4.0 4.5 4.5 5.0 5.0 5.0 3.0 5.5 2.0 1.0 4.0 6.0 4.0 2.0 8.0 9.0 6.5 4.5 TYP 125 6.0 7.0 6.5 6.5 6.5 6.5 5.0 7.5 4.0 2.5 6.0 8.0 6.0 4.0 9.5 11.0 8.5 6.5 9.0 9.5 9.0 9.0 9.5 9.5 8.0 10.5 6.5 5.5 9.0 11.0 9.0 7.0 12.5 14.0 11.5 9.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 90 4.0 4.5 4.5 5.0 4.5 4.5 3.0 5.0 2.0 1.0 3.5 5.5 3.5 2.0 7.0 8.0 5.5 4.0 10.0 10.0 10.0 9.0 10.0 10.0 9.0 11.0 7.5 6.0 10.0 11.5 10.5 7.5 14.0 16.0 13.0 10.5 MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1988 Apr 22
6
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) tREC Setup time, High or Low RE to CP Hold time, High or Low RE to CP Setup time, High or Low D0, D1 or I/On to CP Hold time, High or Low D0, D1 or I/On to CP Setup time, High or Low SE to CP Hold time, High or Low SE to CP Setup time, High or Low S/P to CP Setup time, High or Low S to CP Hold time, High or Low S or S/P to CP CP Pulse width, High or Low MR Pulse width, Low Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 2 8.0 12.5 0 0 4.0 4.5 0 0 5.5 5.0 0 0 10.5 9.5 4.0 8.5 0 0 5.0 5.0 5.0 4.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 9.5 14.0 0 0 6.0 5.0 0 0 7.0 5.5 0 0 11.0 10.5 4.5 9.5 0 0 5.0 5.0 5.0 4.5 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1988 Apr 22
7
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX MR CP VM tW(H) tPHL Q7, I/On VM tW(L) tPLH VM Q7, I/On CP tPHL VM VM tW(L) tREC VM VM VM
SF00878
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF00879
Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time
RE, D0, D1, I/On, SE, S/P, S
RE, S/P, OE VM ts(H) VM th(H) VM ts(L) VM th(L) VM I/On
VM tPZH VM
VM tPHZ VOH -0.3V
CP
VM
0V
SF00880
SF00881
Waveform 3. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
RE, S/P, OE
VM tPZL
VM tPLZ VM VOL +0.3V
I/On
SF00882
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1988 Apr 22
8
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1988 Apr 22
9
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